Product category: Design Services
News Release from: Cadence Design Systems | Subject: Engineering services
Edited by the Electronicstalk Editorial Team on 1 September 2004
Stretch shrinks time to market
Cadence Design Systems has helped enable Stretch to meet an aggressive time-to-market goal for a high-performance software-configurable processor design
Stretch benefited from the strength of a comprehensive Cadence digital IC design flow and libraries from Taiwan semiconductor manufacturing Company (TSMC), to mitigate its design risks and ensure high quality of silicon (QoS) through improved area and performance. "Cadence was instrumental in our successful effort to implement this tapeout on schedule", said Wayne P Heideman, Vice President of Engineering at Stretch, provider of a family of software-configurable processors.
This article was originally published on Electronicstalk on 1 September 2004 at 8.00am (UK)
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"The Cadence Encounter platform's world-class technology and methodologies, combined with the innovative Cadence VCAD service model and the TSMC-developed libraries, gave us the edge we needed to minimise our design time and achieve the QoS we required".
Drawing on the Cadence Encounter digital IC design platform, Cadence engineering services worked closely with Stretch as it took the design from netlist to GDSII.
The breakthrough, 4-million-plus-gate design featured multiple clocks, custom programmable datapaths, and extensive high-speed I/Os.
It was targeted to TSMC's 0.13-micron process and employs TSMC standard cell libraries available with the Cadence Encounter design platform.
"Through our collaboration with Cadence, TSMC is able to offer customers like Stretch a variety of process-tuned libraries for high-speed and low-power designs", said Edward Wan, Senior Director of Design Services Marketing for TSMC.
"Using the TSMC-developed libraries as an integrated part of the Cadence Encounter platform provided Stretch with an accelerated path to volume silicon".
"Integration of the Cadence Encounter IC digital implementation system, TSMC's silicon-validated libraries, and Cadence engineering services, gives customers a real time-to-market advantage", said Lavi Lev, Executive Vice President and General Manager of Cadence Design Systems' Implementation Division.
"Our VCAD service model provides a virtual CAD and collaborative design environment in which our customers work with Cadence and take advantage of our specialised expertise to achieve their design goals".
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