Product category: Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial Team on 16 January 2004
Incisive decision for eInfochips
eInfochips has adopted the Cadence Incisive verification platform to meet its advanced design and verification requirements
As a leading developer of reusable verification components and intellectual property (IP), eInfochips required a solution for system-level and register transfer-level (RTL) verification. The company will use the Cadence Incisive platform in its ASIC design division. Through its work with eInfochips, Cadence continues to connect globally with customers in the design chain.
This article was originally published on Electronicstalk on 16 January 2004 at 8.00am (UK)
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"As a technology company dealing with SystemC designs, it is paramount that we have a design environment where we can simulate SystemC blocks with RTL.
It is imperative that simulation performance and the detailed code coverage capability are excellent", said Samir Shroff, Director of the ASIC Design Division at eInfochips.
"The successful deployment of Incisive in our IP Cores development effort led us to adopt Incisive in our ASIC design services division, as well".
"The Incisive verification platform is the industry-leading solution for mixed language simulation.
The Incisive platform builds on our long history of technical innovation success, offering the ultimate simulation speed and efficiency, reducing testbench development and debug time and increasing RTL performance", said Himanshu Singh, Executive Director, India and SAARC, Cadence Design Systems.
"We are committed, on a global basis, to providing customers like eInfochips with the most comprehensive platforms on the market to address their advanced verification and SystemC design needs".
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