Click on the advert above to visit the company web site

Product category: Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial Team on 7 January 2004

Cypress standardises on extractor

Cypress Semiconductor has adopted the latest version of the Fire and Ice QXC as the signoff cell-based extractor in its 130 and 90nm production flows

The Fire and Ice QXC extractor, part of the Cadence Encounter digital IC design platform, with its new generation 3D scanning engine and models, delivers an accurate method of accounting for all significant copper and optical effects. These enhancements enable designers to reduce timing margins and achieve first silicon success, helping accelerate the time from chip design to volume production.

"We are currently using Fire and Ice QXC in the design of some very advanced chips, including the Ayama family of network search engines, and have found the latest release to be extremely effective", said Paul Keswick, Senior Vice President of Cypress's New Product Development (NPD) group.

"It delivers the accuracy we need to confidently address the optical and copper effects that have become serious design issues in our 130 and 90nm flows.

The accuracy of extraction results for processes that have air gaps was a deciding factor in Cypress selecting Fire and Ice QXC as our signoff gate-level extractor".

Cypress engineers found that Fire and Ice QXC easily beat their accuracy requirements, producing results within 6% of a reference field solver.

Keswick added: "What impressed us most was the near-zero mean and standard deviation of less than 2%.

Accuracy like this translates to less over-design and shorter design cycles".

"Customers designing complex chips for 130 and 90nm processes have asked us for help in addressing the significant yield problems that copper and optical effects pose", said Marc Levitt, Vice President of the DFM product line, Cadence Design Systems.

"Our response, Fire and Ice QXC, has been validated by leaders in the silicon design chain to be the most accurate cell-based extractor on the market, and Cypress' adoption of this new version is further confirmation that we hit the mark with customers".

Fire and Ice QXC integrates seamlessly with the Cadence Encounter digital IC design platform, including Cadence timing and signal integrity analysis and power verification solutions (SignalStorm, CeltIC and VoltageStorm).

Used during place-and-route of complex ASIC/ASSP and SoC designs, Fire and Ice QXC extracts interconnect parasitic data directly into the SoC Encounter timing database format for timing and signal integrity analysis or in standard detailed standard parasitic format (DSPF) or standard parasitic exchange format (SPEF).

Fire and Ice QXC also integrates easily with any standard place-and-route or analysis flow via industry standard file formats.

Fire and Ice QXC is available now.

• Cadence Design Systems: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• NEW
• Electronicstalk Home Page

Search the Pro-Talk network of sites

Put your news on Electronicstalk  |   Advertise  |   Get the free Electronicstalk newsletter
Electronicstalk Home  |   About Electronicstalk  |   Copyright © 2000-2007 Pro-Talk Ltd, UK