Product category: Design and Development Software
News Release from: Cadence Design Systems | Subject: Tower PDKs
Edited by the Electronicstalk Editorial Team on 27 June 2003
PDKs reduce risk
and simplify silicon design
The new Tower TSL018 and TSL035 foundry-level process design kits (PDKs) were developed by Cadence Design Systems
The new PDKs eliminate the need for Tower customers to create their own "views" of the Tower technologies in their design environments, thereby reducing design time and risk. Through this development, Tower and Cadence are enabling a key component of the silicon design chain for their mutual customers.
This article was originally published on Electronicstalk on 27 June 2003 at 8.00am (UK)
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"The ability to support custom design methodologies with silicon-validated process design kits is a strong benefit to companies working with these complex designs", said Sergio Kusevitzky, Vice President of IP and Design Services, Tower Semiconductor.
"Cadence's track record of expertise and commitment to customer support has proved to be the most effective choice for our customers".
The PDKs include a device and symbol library, technology file, physical verification decks, and design-rule-correct parameterised cells (P-cells) to automate device layout.
The PDKs are compatible with the Cadence Spectre models provided by Tower Semiconductor and are tailored for use in the Cadence RF/analogue mixed-signal design solution consisting of AMS Designer, Composer, Analog Design Environment, Spectre/Spectre-RF, Virtuoso Layout Editor and XL, Custom Router and the Assura/Diva physical verification suites.
"The development work with Tower Semiconductor demonstrates our on-going commitment to the foundry market and the silicon design chain.
The PDKs we have supplied provide a silicon foundation for Tower customers to design in the Tower process", said Guillaume d'Eyssautier, Senior Vice President and General Manager, Europe, Cadence Design Systems.
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