Product category: Design and Development Software
News Release from: Cadence Design Systems
Edited by the Electronicstalk Editorial Team on 4 February 2003
First Encounter for STMicroelectronics
STMicroelectronics is to use Cadence First Encounter for silicon virtual prototyping of its SoC designs at 90 and 130nm silicon geometries.
Note: Readers of the free Electronicstalk email newsletter get to read news like this as soon as it is announced. Find out how to register for your free copy now.
STMicroelectronics is to use Cadence First Encounter for silicon virtual prototyping of its SoC designs at 90 and 130nm silicon geometries. The company will use First Encounter, a key nanometre technology included in the Encounter platform, to ensure design success and shorten time-to-market on very complex integrated circuits. At nanometre geometries, interconnect plays a vital role in determining chip performance.
ST design engineers will use First Encounter to quickly generate and rapidly refine an accurate virtual prototype of their IC physical design, including its interconnect.
The prototype provides fast feedback on chip performance and a fully functional, physically feasible layout.
This in turn will help ST's design teams produce a signoff-quality floor plan and preliminary placement optimised for rapid, reliable design closure.
Using First Encounter will help ST continue to stay ahead of its competitors in delivering leading-edge, high-value products to its customers and allows ST to define a new interface with ASIC customers.
First Encounter will be used to drive both Cadence and third-party tools for detailed chip implementation.
"ST is moving aggressively to leverage cutting-edge silicon technologies and design methodologies", said Ping Chao, Senior Vice President and General Manager of the Digital IC group at Cadence.
"We're pleased to have been selected for this advanced design flow.
First Encounter quickly establishes a physically feasible design approach, enabling users to complete even demanding designs rapidly and predictably".
"Our evaluations indicated the First Encounter approach has clear advantages, especially at nanometre geometries", said Philippe Magarshack, Group Vice President for Design Automation, Central Research and Development at STMicroelectronics.
"The silicon virtual prototype produces realistic views of the chip in a shorter time than other methods we've seen, significantly speeding up the physical design flow".
• Cadence Design Systems: contact details and other news
• Email this news to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Related Stories
STMicroelectronics uses Cadence VCC methodology
STMicroelectronics has selected the Cadence Virtual Component Co-Design (VCC) for both its automotive and digital consumer platform system-level design methodology and design flow.
Router adds intelligence to automation
Revolutionary technology provides PCB designers with an automated, intelligent planning and routing environment.
Tool detects issues in design constraints
Faraday Technology Corp uses Encounter Conformal Constraint Designer technology to validate customers' design constraints, ensuring the quality of the design before implementation.
Design flow adds assertion-based formal analysis
3Leaf Networks has incorporated the Cadence Incisive Formal Verifier into its overall design flow for assertion-based formal analysis.
Verification and custom businesses lead growth
Cadence Design Systems has reported fourth quarter 2006 revenue of US $431 million, an increase of 14% over the $378 million reported for the same period in 2005.
Search the Pro-Talk network of sites
