Product category: Embedded Software and Operating Systems
News Release from: Bops | Subject: Halo C compiler
Edited by the Electronicstalk Editorial Team on 16 October 2001

Saintly performance from DSP C compiler

Bops is claiming breakthrough DSP performance on the industry-standard EEMBC TeleMark benchmark suite for optimised C compilation using the Halo C compiler

Bops is claiming breakthrough DSP performance on the industry-standard EEMBC TeleMark benchmark suite for optimised C compilation using the Halo C compiler, as certified by the independent testing organisation EEMBC Certification Laboratories (ECL). The Bops Halo C compiler, which efficiently maps high-level C code onto the Bops ManArray parallel architecture, achieved a certified TeleMark score of 139.8 for optimised C code.

"Not content with its previous score of 26.7 EEMBC TeleMarks for optimized C, Bops had ECL certify their new score of 140", said Alan R Weiss, ECL chairman and chief technical officer.

"This outstanding score was achieved in a fairly short amount of time and shows the progress their Bops Halo C compiler is making towards exploiting the ManArray architecture.

The underlying processor, a Bops Manta 2x2 136MHz part, did not change between the previous certification and this new score", he said.

"It will be interesting to see how Bops' competition will score with new products as the white-hot race in DSP performance heats up".

"With its release of new EEMBC telecomm benchmark scores, it became obvious that the Bops ManArray architecture and Halo C Compiler can deliver great performance without having to resort to hand-coded assembly", stated Markus Levy, MicroDesign Resources senior analyst.

"The ability to use a compiler to extract the performance out of a parallel processing, VLIW-based architecture is a credible feat".

"Most DSP algorithm data flows are inherently parallel, so programmable processors that can simultaneously exploit all three levels of parallelism with a low-latency communication fabric have natural advantages", explained Steven E Schulz, vice president of corporate marketing for Bops.

"The lower clock rates made possible by the ManArray parallel architecture not only eases timing and signal integrity concerns, but more importantly results in lower power consumption and lower cost.

The ability of designers to take advantage of that from high-level C code is truly a breakthrough for the industry".

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