News Release from: Bops
Edited by the Electronicstalk Editorial Team on 23 May 2001

Low-power DSP cores deliver 100MIPS/mW

Bops has released a range of low-power-consumption DSP cores designed to extend battery life without giving up the high performance required by the next-generation of mobile devices.

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Bops has released a range of low-power-consumption DSP cores designed to extend battery life without giving up the high performance required by the next-generation of mobile devices. "The problem system designers of mobile broadband wireless devices have to deal with today is the trade-off required between power and performance: higher performance typically requires more power", explained Mark Bowles, president and COO, Bops. "Bops newest cores solve this problem by delivering 100MIPS/mW or more than five times the performance of existing low-power DSP chips.

Ours is the disruptive technology needed to break the chokepoints that exist today in getting broadband data and high-quality video onto cell phones, PDAs and handheld personal computers". All Bops low-power cores achieve an industry-leading 0.01mW/MIP (16bit RISC equivalent MIPS).

Performance of cores range from 1000 to 4000MIPS and power consumption for cores, not including memories, range from 11 to 36mW, allowing customers to select cores with optimum balance of cost, performance, and power for their specific application.

All low-power cores act as thread co-processors to ARM, MIPS, and other industry-standard low power CPUs.

As thread coprocessors, Bops new cores are capable of handling multiple communications and imaging threads independent of the RISC CPU and thus provide superior power efficiency and performance headroom compared to single RISC implementations with DSP extensions.

The new cores take advantage of Bops ManArray architecture's inherently low-power parallel architecture, low-power RTL design techniques, and SRAM design techniques.

During the design process, Bops used best-in-class design tools to minimise power consumption of its low-power cores.

Synopsys' Power Compiler was used to deliver "pushbutton" power optimisation, achieving 40% power reduction automatically.

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