Product category: Design and Development Software
News Release from: Blaze DFM | Subject: Blaze IF
Edited by the Electronicstalk Editorial Team on 12 December 2006
Fill synthesis meets foundry CMP rules
Blaze IF optimally meets complex CMP design rules without requiring complicated scripts, and without harming chip performance or power
Blaze DFM is broadening its suite of electrical DFM products with the introduction of the Blaze IF fill synthesis tool. Blaze IF optimally meets complex CMP design rules without requiring complicated scripts, and without harming chip performance or power. Blaze IF inserts 'dummy' fill patterns into the design layout to reduce topographical variations that occur as a result of chemical mechanical polishing (CMP) during the manufacturing process.
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Failure to meet surface topography variation constraints causes defocus and pattern dimensional error in lithography, degraded transistor characteristics in the case of shallow trench isolation (STI), and electrical shorts or increased wire resistance in the case of metal interconnects, all of which are detrimental to circuit yield.
Blaze IF is based on the trailblazing fill synthesis research of University of California at San Diego professor Dr Andrew B Kahng, cofounder and Chairman of Blaze.
'The fill solutions produced by Blaze IF optimally meet foundry CMP rules', said Dr Kahng.
'Blaze IF results are literally unbeatable - if there is a fill solution that meets foundry requirements, Blaze IF will find it, and the solution found by Blaze IF will be the best achievable'.
'On the other hand, if Blaze IF cannot find a feasible solution, then no solution exists'.
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Without Blaze IF, engineers must perform fill synthesis using custom scripts written for design rule verification tools.
The advancing complexity of CMP design rules has caused fill insertion scripts to become overwhelmingly complex, to the point that it is impractical to maintain such an approach going forward.
As a tool specifically designed to handle advanced foundry CMP design rules, Blaze IF is much easier to maintain and use than the impractical 'script-ware' being used today.
Blaze IF supports all modern CMP design rules, including allowed density upper and lower bounds, density smoothness constraints, dummy via insertion, dimension constraints and pattern types for dummies, dummy-to-dummy spacing, and spacing between dummies and functional trenches or wires, based on the planarity requirements for the inter-layer dielectric (ILD) overlying the metal.
Blaze DFM was the first to introduce a new generation of 'electrical DFM' solutions with the announcement of the company and the release of Blaze MO leakage power optimisation software in May 2006.
Following in the footsteps of Blaze MO, Blaze IF uses a chip's power and timing requirements to elevate fill to a level beyond the shape-centric approaches of the past.
Blaze IF uses the Blaze timing and power analysis engines to maintain power and performance requirements while the fill shapes are being added.
The result is that it ensures that foundry fill requirements are met while preserving timing correctness and minimising the impact on dynamic power.
Blaze IF underwent extensive beta testing at a number of companies including Cypress Semiconductor.
Cypress used Blaze IF to optimise the planarity of a high-speed sensor chip.
The goal was to limit variations in inter-layer dielectric thickness to 30%.
The actual result achieved was 13%.
The results were first verified through CMP simulation, and then validated in silicon.
'Blaze IF offers a number of advanced fill synthesis techniques that we require for our leading-edge devices', said Dr Artur Balasinski, Principal Engineer at Cypress.
'We worked together with the Blaze engineers to validate Blaze IF results in silicon on a product chip and they exceeded our expectations by a wide margin'.
Blaze IF is available immediately on 32 and 64bit Red Hat Linux and 64bit SUSE Linux.
List pricing starts at US $250,000 per year.
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