News Release from: Berkeley Design Automation
Edited by the Electronicstalk Editorial Team on 9 May 2006

Software closes the analysis gap for Elpida

Elpida Memory uses PLL Noise Analyzer to guarantee the high performance, low noise and low power specifications for the phase-locked loops in its advanced memory chips.

Note: Readers of the Editor’s free email newsletter will have read this news when it was announced. . It’s free!

Berkeley Design Automation is celebrating the adoption and successful deployment of PLL Noise Analyzer. Elpida Memory has attained the high performance, low noise and low power specifications for the phase-locked loops (PLLs) in its advanced memory chips by using the fast and accurate noise analysis and diagnostic capabilities provided by Berkeley Design's Precision Circuit Analysis technology. 'Elpida's advanced memory devices run at very high clock rates and must meet very tight noise specifications', said Yoshitaka Kinoshita, Product Development Officer at Elpida.

'The ability of PLL Noise Analyzer to provide fast and accurate transistor-level jitter analysis for the PLLs in our designs before tape-out enabled us to reduce the number of silicon prototype cycles and thereby accelerate our time to volume'.

DRAM products must meet high performance and low power specifications, while also providing high capacity.

With traditional analogue/RF analysis methodologies and tools, there is a gap between what the designers observe in simulation compared with the actual silicon measurements - this is called the analysis gap.

This gap makes it necessary to produce multiple silicon prototypes to accurately characterise these designs, resulting in delayed time to volume and increased product development costs.

Berkeley Design Automation has developed next generation circuit analysis technologies, called Precision Circuit Analysis (PCA), to close the analysis gap by allowing designers to accurately characterise their designs before tape-out.

PLL Noise Analyzer, the company's first product, is the industry's only tool that accurately characterises the noise and jitter performance of nonlinear circuits, such as PLLs and VCOs, at the transistor level.

Berkeley Design's proprietary Stochastic Nonlinear Engine, a key component of the PCA technology and the foundation of PLL Noise Analyzer, provides fast and accurate analysis of the nonlinear, time-varying behaviour of full PLL circuits at the transistor level.

By supporting standard HSpice and Spectre netlist and model formats, PLL Noise Analyzer can be easily adopted into existing verification flows.

'We are excited that Elpida has chosen PLL Noise Analyzer to verify the noise performance of the PLLs in its most advanced memory devices', said Ravi Subramanian, President and CEO of Berkeley Design Automation.

'Our Precision Circuit Analysis technology provides incredible speed and accuracy that allows companies such as Elpida to reduce silicon re-spins and get their chips to volume production on time'.

• Berkeley Design Automation: contact details and other news
• Other news in Design and Development Software
• Email this news to a colleague
•
• RSS news feed for Berkeley Design Automation
• RSS news feed for Design and Development Software
• Electronicstalk Home Page

 
Advertisers! Download our free 2006 media pack now