Programme to speed SystemVerilog integration

Beach Solutions has joined Synopsys' SystemVerilog Catalyst Programme.

Beach Solutions has joined Synopsys' SystemVerilog Catalyst Programme.

Beach Solutions plans to provide full support for Accellera's SystemVerilog 3.1 language standard in its EASI-Studio product.

By participating in Synopsys' SystemVerilog Catalyst Program, Beach Solutions gains early access to Synopsys' SystemVerilog-based tools, including VCS HDL Simulator and HDL Compiler, the front-end language compiler for Design Compiler.

This access helps to ensure consistent support of the SystemVerilog language and interoperability between Synopsys' tools and Beach Solutions' Easi-Tools product suite.

"SystemVerilog is aimed at covering both the design and verification of complex SoC and embedded systems devices", said Terry McCloskey, CEO of Beach Solutions.

"Since its formation, Beach Solutions have been delivering tools that ease the re-use and integration of IP for such devices - goals that are aligned with the benefits that can be derived from the adoption of the SystemVerilog design language".

Beach Solutions plans to provide full support for SystemVerilog 3.1 in its Easi-Studio product in a similar way that it does for VHDL and Verilog.

From a specification that defines the IP block interfaces and system-level interconnects in any SoC, Easi-Studio is able to produce synthesisable hardware code along with verification test benches for the target architecture.

Users have the choice of which language and style in which generated code is to be represented complementing their chosen tool flow.

These options will now include SystemVerilog.

With its Easi-Studio product, Beach Solutions has been unifying SoC design flows, specifically reducing the gap between the hardware and software development and the design and verification in both these areas.

Based around a third-generation schema specifically for describing SoC interfaces, Easi-Studio promotes a re-use methodology through the automatic generation and consistent presentation of design data from a validated, centralised specification.

Working alongside existing design flows, this approach reduces design discrepancies caused by misinterpretation or miscommunication between the different design disciplines.

"Fully supporting SystemVerilog 3.1 is a natural step in the evolution of our products", McCloskey continued.

"In order for today's complex SoC designs to be successful, an effective design re-use strategy is essential.

Our tools facilitate the easy adoption of design re-use strategies within existing design flows.

This applies equally to IP for hardware design, software design and test.

Adding SystemVerilog to our Easi-Tools family is a significant addition to range of design flows we support".

"Synopsys' SystemVerilog Catalyst Programme is a growing community of over 30 electronic design automation (EDA) vendors, silicon and verification IP companies, and training service providers helping to ensure that our customers experience the interoperability and design quality benefits of SystemVerilog", said Rich Goldman, Vice President, Strategic Market Development at Synopsys.

"The momentum behind SystemVerilog is exceeding our expectations.

The more the design community and the EDA industry collaborate on interoperability initiatives, the more successful our mutual customers can become".

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