Product category: Design and Development Software
News Release from: Aldec | Subject: System Verification Environment
Edited by the Electronicstalk Editorial Team on 10 November 2006
Verification environment moves up to
Stratix III
Aldec has announced System Verification Environment (SVE) support for Altera Corporation's new high-end Stratix III FPGA device family.
Aldec has announced System Verification Environment (SVE) support for Altera Corporation's new high-end Stratix III FPGA device family SVE supports all aspects of system-level design development and verification
This article was originally published on Electronicstalk on 21 May 2003 at 8.00am (UK)
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