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Product category: Design and Development Software
News Release from: Aldec | Subject: Riviera 2005.04
Edited by the Electronicstalk Editorial Team on 19 April 2005
New technology speeds system-level
verification
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The latest release of Riviera features an all new system-level simulation engine and improved SystemC debugging.
Aldec has released Riviera 2005.04 with an all new system-level simulation engine and improved SystemC debugging Riviera is based on Aldec's industry-proven VHDL and Verilog mixed-language simulation technology used by ASIC and high-density FPGA designers for new generation system-on-chip designs
This article was originally published on Electronicstalk on 1 Jul 2008 at 8.00am (UK)
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