Product category: Intellectual Property Cores
News Release from: ARM | Subject: Cortex-R4F
Edited by the Electronicstalk Editorial Team on 10 October 2006
Processor core meets automotive demands
ARM has released details of its Cortex-R4F processor, designed to reduce the cost and design time of future automotive electronic technology.
ARM has released details of its Cortex-R4F processor, designed to reduce the cost and design time of future automotive electronic technology The Cortex-R4F processor will enable ARM partners to meet the stringent error-free safety standards and high performance requirements of automotive applications including next-generation antilock braking systems (ABS) and vehicle stability systems
This article was originally published on Electronicstalk on 8 Nov 2004 at 8.00am (UK)
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The advanced features of the Cortex-R4F processor specialised for the automotive market include support for error-correcting code (ECC) memory, the extension of error detection into the interconnect and a synthesis-optional floating-point unit (FPU).
"Vehicle OEMs need to continually innovate in order to meet tightening emissions and safety legislation, while adapting to changing consumer expectations", said Chris Webber, Vice President, Automotive Practice, Strategy Analytics.
"The ARM announcement of the Cortex-R4F processor is extremely timely as designers of next-generation automotive control systems look for highly robust floating-point processor solutions that are needed for the innately intelligent backbone which will be part of even the most affordable car".
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"Automotive systems require high performance at the very highest levels of reliability to maintain our stringent safety standards", said Berthold Fehrenbacher, Engineering Manager, of Robert Bosch.
"The Cortex-R4F processor enables Bosch to provide this through extensive features that are closely aligned to our product requirements".
The Cortex-R4F processor builds on the advanced features of the Cortex-R4 processor.
These features include configurability during synthesis to optimise the processor for di