Product category: Intellectual Property Cores
News Release from: ARM | Subject: L210 Level 2 cache controller
Edited by the Electronicstalk Editorial Team on 26 February 2004
Cache controller cuts
processor power drain
When combined with an ARM processor, the ARM L210 Level 2 cache controller has the potential to increase performance by between 25 and 75%, extending battery life and reducing memory cost
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Motorola was the lead partner in the definition of the L210 controller and is the first ARM partner to license it. The ARM L210 controller will be incorporated into Motorola's Mobile Extreme Convergence (MXC) architecture for 2.5G, 2.75G and 3G mobile handsets and a new category of portable multimedia devices.
MXC incorporates an ARM1136JF-S core together with the ARM L210 Level 2 cache controller.
Motorola has been using the ARM architecture in its products for more than three years, enabling the company to develop advanced high-end mobile devices.
Motorola worked closely with ARM to define the optimal cache controller used in the MXC architecture.
Further reading
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Synopsys has announced the immediate availability of a fully automated implementation flow enabled by Synopsys IC Compiler for high-performance and low-power applications
Processor is first specifically for FPGAs
The ARM Cortex-M1 processor is the first ARM processor designed specifically for implementation on FPGAs
The addition of this enhanced memory subsystem typically increases the performance by 25 to 75%.
When incorporated into Motorola's MXC architecture, the ARM L210 controller enhances performance to meet growing consumer demand for powerful next-generation handsets that maintain optimal levels of battery life.
By concentrating all of the modem processing onto a single DSP (single core modem), the MXC architecture is designed to free up the MCU core to enable richer feature sets across a wide range of mobile devices; simplify the software development environment; accelerate time to market; simplify and reduce interprocessor communications; enable increased efficiency via shared and reduced memory requirements; and provide seamless mobility in a small footprint, with low system and development costs.
"This advancement builds on ARM's high performance road map to extend our strength in performance-driven market segments such as the consumer entertainment and wireless markets", said Bruce Beckloff, Director of Segment Marketing, ARM.
"With the addition of the L210 cache controller to a system, ARM enables our Partners to realise the power of our high-performance cores, such as the ARM1136JF-S core in the 550MHz range, without having to implement an expensive and complex memory system that would increase system cost and power consumption".
The L210 cache controller reduces the external memory bandwidth requirement of very high-performance CPUs like the ARM1136JF-S core, by requiring fewer CPU memory accesses to go to off-chip memory.
It uses a unified instruction and data cache, supporting level two cache sizes from 128Kbyte to 2Mbyte.
The L210 controller is compatible with the ARM1136JF-S core, the ARM1136J-S core, the ARM1026EJ-S core and the ARM926EJ-S core.
The ARM L210 Level 2 cache controller is available for licensing from ARM immediately.
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