Product category: Analogue and Mixed Signal ICs
News Release from: Analog Devices | Subject: AD9444
Edited by the Electronicstalk Editorial Team on 12 January 2005
Big SFDR suits
ADC to basestation duties
A new 14bit, 80Msample/s analogue-to-digital convertor is billed as having the highest spurious-free dynamic range in its class
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A new 14bit, 80Msample/s analogue-to-digital convertor (ADC) is billed as having the highest spurious-free dynamic range (SFDR) in its class. With wireless communications providers now carrying multiple radio standards, SFDR has become increasingly important for increasing call capacity and reducing dropped calls.
The first in a family of high-speed, high-resolution ADCs optimised to improve the robustness and simplify the design of advanced 3G and next-generation 4G wireless basestations, the AD9444 provides a typical SNR of 73.1dB and SFDR of 97dBc with a 70MHz input - a full 7dB better than any other ADC in its class.
Optimised for wireless basestation applications, its high SFDR also makes the AD9444 well suited to test equipment, wireless broadband and high-end data acquisition systems.
'The implementation of multicarrier radio architectures in 3G has magnified the importance of SFDR to wireless systems designers', said Kevin Kattmann, product line director of the High-Speed Convertor Group at Analog Devices.
'To increase the capacity within a cell site and improve the quality of service per basestation cell, 3G multicarrier wireless designers require the high-performance receiver technology the AD9444 enables'.
SFDR is a key specification used to qualify the performance of an ADC.
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A convertor with a high SFDR can capture weak signals in the frequency band of interest, despite the presence of stronger signals.
The 97dBc SFDR of the AD9444 ADC expands the dynamic range of wireless basestation receivers, while improving quality of service and lowering cost.
In addition to delivering 97dBc SFDR and 73.1dB SNR with a 70MHz input, the AD9444 provides high accuracy, with typical differential nonlinearity (DNL) of +/-0.4LSB, integral nonlinearity (INL) of +/-0.6LSB, and power dissipation of 1.2W.
The ADC also features parallel low-voltage differential signalling (LVDS) outputs, including an output clock, simplifying the interface to digital downconvertors and reducing the potential for digital noise coupling back into the ADC core.
The AD9444 is the first device in a family of Analog Devices' high-speed ADCs that will offer higher sample rates, ease of use and improved dynamic performance at competitive prices.
The LVDS output of the AD9444 interfaces seamlessly with the LVDS support of the AD6636 multichannel wideband digital downconvertor, which is optimised for Analog Devices' TigerSHARC digital signal processor.
Additionally, a clean clock source for the AD9444 is obtained when the device is used with the AD9510 high-performance clock distribution integrated circuit.
The AD9444 is an ideal companion to Analog Devices' industry-leading TxDAC+ portfolio of digital-to-analogue convertors and VersaCOMM digital down- and upconvertors.
Together, these devices form the basis for a high-performance digital radio transceiver.
The AD9444 ADC is shipping in production volume now, available in Pb-free 100-lead TQFP-EP (thin quad flatpack exposed paddle) and priced at $38.25 per unit in 1000-unit quantities.
The device is supported by two evaluation boards and a behavioural model that can be used with Analog Devices' ADIsim ADC modelling software.
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