Product category: Intellectual Property Cores
News Release from: Avago Technologies | Subject: Third-generation serdes core
Edited by the Electronicstalk Editorial Team on 04 January 2005
Serdes core shrinks to work at 90nm
Agilent Technologies has validated its third-generation serdes core in a 90nm CMOS process technology.
Agilent Technologies has validated its third-generation serdes core in a 90nm CMOS process technology Due to the core's superior noise immunity, modular design and low power consumption, storage and networking OEMs are now able to embed as many serdes channels (each operating at up to 6.25Gbit/s) as needed onto a single ASIC chip
This article was originally published on Electronicstalk on 8 Nov 2004 at 8.00am (UK)
Related stories
High brightness on surface mount LEDs.
Agilent Technologies has introduced a series of surface-mount LEDs designed and qualified specifically for automobile interior and exterior lighting applications.
Hot-pluggable transceiver for Fibre Channel
Agilent Technologies has announced volume availability of its 2Gbit/s small-form-pluggable (SFP) fibre-optic transceiver for Fibre Channel storage area networks (SANs).
"Our latest 90nm validated serdes core offers customers the flexibility to embed hundreds of serdes channels on a single chip", said Kin Chan, Director of Engineering for the Networking Solutions Business Unit in Agilent's Semiconductor Products Group.
"Agilent's unrivaled combination of high-performance IP cores, high-speed design and embedded test expertise is what maintains our position among the ASIC leaders".
In tests conducted at Agilent, the embedded serdes ASIC achieved error-free transmission driving signals over FR4 material (at room termperature) a distance of 760mm using two connectors.
The 90nm serdes core is compliant with Ethernet XAUI and is designed to offer these industry-leading features: 1149.6 AC-Extest for testing AC-coupled connections between ICs on the PCB; LC-based oscillator for improved power-supply noise rejection; decision feedback equalisation; BERT on chip for channel optimisation; automatic receiver DFE tuning; low bit error rate of less than 10e-17; and internal 100ohm differential termination.
Agilent's embedded serdes ASIC development model provides support throughout the entire product life cycle.
It incorporates testing capabilities as early as the definition of system-level architecture and accounts for in-circuit manufacturing test, functional test, system turn-on and debug, and field diagnostics.
With this model, Agilent enables equipment manufacturers to develop high-bandwidth networking and storage systems with superior reliability and reduced size, complexity and cost. Request a free brochure from Avago Technologies ...
• Avago Technologies: contact details and other news
• Email this article to a colleague
• Register for the free Electronicstalk email newsletter
• Electronicstalk Home Page
Search the Pro-Talk network of sites
