Product category: Communications ICs (Wired)
News Release from: Avago Technologies | Subject: 36-channel SerDes ASICs
Edited by the Electronicstalk Editorial Team on 19 February 2002
ASICs can handle up to 36 serdes
channels
Agilent Technologies is claiming a new milestone in the integration of serialiser/deserialiser (SerDes) channels in ASICs for communications applications.
Agilent Technologies is claiming a new milestone in the integration of serialiser/deserialiser (serdes) channels in ASICs for communications applications Agilent's results are nine times the current standard in SerDes integration, and are expected to provide manufacturers with a tremendous savings in board space and cost
This article was originally published on Electronicstalk on 8 Nov 2004 at 8.00am (UK)
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Agilent's results were achieved by integrating 36 multirate SerDes channels operating at up to 3.125Gbit/s each, on a single CMOS chip.
These results provide a new level of I/O performance and integration in a CMOS process.
Until today, the former industry standard was four 3.125Gbit/s SerDes channels per chip.
"We continue to raise the bar in ASIC SerDes integration", said Michael Huether, Director of Marketing Europe, Middle East and Africa of Semiconductor Products Group.
"These advancements allow us to provide our customers with tremendous savings in power, board space and cost, and to reduce design complexity".
The multirate ASIC is backward compatible because each SerDes channel is able to operate at link rates down to 1.5Gbit/s.
The device, which incorporates 32 million transistors, can also drive a signal approximately 20m over standard copper cable.
Agilent has previously announced a chip with more than 50 x 2.5Gbit/s SerDes transmit and receive channels, and another ASIC with 16 x 3.25Gbit/s channels. Request a free brochure from Avago Technologies ...
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