Product category: Communications ICs (Wired)
News Release from: Agere Systems | Subject: Network processors
Edited by the Electronicstalk Editorial Team on 02 August 2005
DSPs and network processors in DSL
systems
Dave Sonnier CTO of Agere Systems Telecommunications Division looks at DSL chip architectural debates centred on digital signal processor and network processor integration.
As the various digital subscriber line (DSL) technologies continue to be deployed worldwide, complex silicon integration issues have begun to take centre stage These issues centre on various ways digital signal processor (DSP) modem and network processor chips might be integrated in digital subscriber line access multiplexer (DSLAM) equipment
This article was originally published on Electronicstalk on 23 Mar 2004 at 8.00am (UK)
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To put this context, first a little background.
During the past several years, two methods have been used to lower DSLAM equipment costs.
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First has been increasing DSL channel count (density) per chip.
This means squeezing more processing power into a single chip.
Higher density also means functions of common chips, such as control processors and memory chips, are all spread over more channels, further reducing the cost per channel.
The second method of cost reduction focuses on more functional integration of DSP modem chip and NP functions Today's typical DSLAM offerings consist of two sets of architectures.
The first, a distributed architecture, consists of DSL modems using DSP chips and an NP or communications processor chip per circuit board line card.
This architecture allows carriers to "pay as you grow", because the single line card is functionally a stand-alone DSLAM.
The second, a centralised architecture, uses a much higher performance NP on a common line card, connected to many DSL line cards using a simple backplane interface device.
With DSL line cards moving closer to the user, primarily because DSL line speeds degrade as distance increases, the distributed architecture has a sustainable cost advantage in the long run.
The reason is because smaller density DSLAMs are ultimately a single circuit board, which could be mounted in a small pizza-box-type enclosure or small rack.
The centralised architecture requires a rack, a common card and a DSL modem card.
More equipment means higher costs.
DSLAM manufacturers are enhancing their DSL modem DSPs with basic processing capabilities to differentiate themselves from competitors who don't.
For example, they are integrating segmentation and reassembly (SAR) functions and traffic management, NP functions on the DSP.
This trend raises several key economic and performance issues.
First, these combined DSL modem and NP offerings could actually decrease channel density and increase DSLAM costs.
One reason is memory chips and associated software will be required to work with each individual DSP rather than share their functions across all modem DSPs.
As a result, ultimately more memory chips would be required to support the combined DSP DSL modem and NP functions than if the NP remains separate on the line card.
More chips means higher costs.
Furthermore, integrating the SAR and NP functions on the DSL modem DSP does not necessarily handle the programmable, IP-centric processing functions above asynchronous transfer mode that many DSLAMs have to perform.
The additional horsepower required would likely spread memory chip and software resources too thin, decreasing channel density.
So a separate, full function NP with more capabilities, such as granular traffic management and flexible protocol processing, would still be required.
It makes more sense to aggregate all functions and services in the NP.
DSPs are tailored for integrating and increasing channel density and speed.
They are not designed to increase DSL service capabilities, such as better network resiliency, more granular traffic management, more per-service guarantees, and more flexibility to handle new service opportunities.
NPs excel at such functions.
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