Product category: Reference Designs
News Release from: Altera Europe | Subject: SerialLite reference design
Edited by the Electronicstalk Editorial Team on 13 February 2004
SerialLite reference design for FPGAs
Altera and Innocor have developed an open source reference design for the SerialLite protocol
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Innocor, an Altera Megafunction Partner Programme member, optimised the SerialLite reference design for Altera's Stratix GX devices. The reference design provides designers with a quick solution for applications implementing high-speed serial links on backplanes. The SerialLite reference design is available for free, as open-source Verilog, with an open-source test bench and complete documentation.
Key features include a point-to-point serial packet-based protocol, low overhead, and an optional retry-on-error for priority packets, unavailable in any other reference design.
"Leveraging their expertise with communications protocols, Innocor has developed a modular reference design that highlights the scalability of SerialLite", said Craig Lytle, Vice President of the Intellectual Property Business Unit at Altera.
"This reference design enables designers to implement SerialLite quickly and effectively".
"We worked closely with Altera to develop the SerialLite open-source reference design which significantly reduces the design time necessary to bring up high-speed serial interfaces", said Randy Gill, President of Innocor.
"Designers can implement SerialLite in Altera's Stratix GX devices using less than two percent of the available logic-leaving a huge percentage of the device for the designer to work with".
The SerialLite reference design is available for free and can be downloaded from the Altera website.
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