Product category: Design and Development Software
News Release from: Actel Europe | Subject: Libero version 6.2
Edited by the Electronicstalk Editorial Team on 14 July 2005

FPGA design suite gets to grips with
timing

A new integrated design environment integrates best-in-class design tools to enable FPGA designers to achieve the highest results in terms of quality, efficiency and functionality.

Detailing significant new functionality for design analysis and timing closure, Actel has introduced its Libero version 6.2 integrated design environment (IDE), which integrates best-in-class design tools to enable field-programmable gate array (FPGA) designers to achieve the highest results in terms of quality, efficiency and functionality With Libero 6.2, Actel unveils its new SmartTime static timing analysis environment, enabling customers to analyse and manage timing constraints, perform advanced timing verification, and ensure predictable timing closure through a tight integration with timing-driven place and route