Product category: Design and Development Software
News Release from: Actel Europe | Subject: Libero 2.1
Edited by the Electronicstalk Editorial Team on 4 March 2002
FPGA design environment
extends to new generation
Actel has launched Libero 2.1, its next-generation integrated design environment, supporting ProASIC Plus Flash-based FPGAs with up to 1 million gates
The devices have been designed as flexible replacements for ASICs and the integrated design environment enables designers to take advantage of the new features of ProASIC Plus devices, such as higher densities, multiple phase-locked loops, in-system programmability, increased memory and user-configurable I/Os.
This article was originally published on Electronicstalk on 4 March 2002 at 8.00am (UK)
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To tie in with this launch Actel has also announced that its Libero Silver and Platinum evaluation versions are available for the first time as free downloads from the Actel website.
Libero Silver offers tool support from entry to programming for Actel devices of 10,000 gates or less, such as Actel's eX family and the ProASIC A500K050.
Libero Silver does not include simulation, but designers may use their own simulator without restrictions.
Further reading
FPGAs take control of LCD panels
Options appeal to designers of power-sensitive portable and handheld consumer, industrial, medical, automotive and military devices that use small- to medium-size LCDs
Design environment helps cut power consumption
The enhanced analysis environment is the first to give users a comprehensive understanding of power usage in all functional modes of the design
The Platinum evaluation version includes all the integrated tools, functionality and power the full Platinum version without the programming capability.
A comprehensive design environment, Libero integrates industry-leading design tools and streamlines the design flow; manages all design, run and report files; and passes necessary design data between tools.
Libero supports mixed-mode design entry input, giving designers the choice of mixing either high-level VHDL or Verilog HDL language blocks with schematic modules within a design.
This capability is especially valuable for designers integrating intellectual property (IP) into complex FPGAs where time-to-market and productivity requirements are stringent.
Libero includes best-in-class tools such as Innoveda's ViewDraw schematic capture tool; SynaptiCAD's WaveFormer Lite test bench generation system; Mentor Graphics' ModelSim simulation and design verification software; Synplicity's Synplify 7.0.3 synthesis software; and Actel's Designer Series place-and-route software and Silicon Explorer verification and logic analyser tool.
ModelSim provides the highest level of simulation support and features regression test support, powerful debug capabilities and superior memory utilisation for simulating a broad range of designs.
ModelSim Actel Edition was designed to both strengthen and fit seamlessly into Actel's design environment.
Synplify software's new high-performance timing engine and device-specific mapping technology provides synthesis technology with extremely fast runtimes and the ability to synthesise high capacity designs, allowing designers to bring their complex FPGA products to market quickly.
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