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News Release from: Accellera
Edited by the Electronicstalk Editorial Team on 24 August 2007
Verification library receives approval
Accellera's Open Verification Library improves electronic design verification when using hardware description languages
Accellera's Board of Directors has approved Accellera's Open Verification Library (OVL) 2.0 as an Accellera verification standard last month. OVL improves electronic design quality and supports Assertion-Based Verification (ABV) with Verilog, SystemVerilog, VHDL and the Property Specification Language (PSL).
This article was originally published on Electronicstalk on 24 August 2007 at 8.00am (UK)
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The Accellera OVL standard includes a library of assertion checkers provided as an open standard.
It improves electronic design verification when using hardware description languages (HDLs) and results in better quality designs by enabling effective use of ABV methodologies.
'Our Open Verification Library 2.0 standard is an open source version of assertion checkers, allowing re-use in various verification environments', said Shrenik Mehta, Accellera Chair.
'The open standard is part of a growing series of Accellera's evolving electronic design language standards, like SystemVerilog and PSL that improve verification and design quality by enabling powerful verification methodologies'.
'OVL has been used for five years as a vendor-neutral and language-independent assertion methodology to functionally verify designs in simulation and formal verification environments'.
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'OVL version 2.0 represents a major step forward for users, while still being fully backwards compatible with earlier versions', said Mike Turpin, Accellera OVL Technical Subcommittee Chair.
'A powerful new feature in OVL is the ability to synthesise assertions into emulators, accelerators and FPGA prototyping environments, extending assertion-based verification with OVL to support the full verification flow, with simulation, formal verification, hardware-assisted verification and FPGA prototyping', added Kenneth Larsen, Accellera OVL Technical Subcommittee Co-chair.
Version 2.0 adds synthesisable checkers that include 'enable' and 'fire' ports for additional control of the checkers when used in hardware flows including emulation, FPGA prototyping or ASIC error detection.
There are also 17 new and more advanced checkers, taking OVL to a total of 50 assertion checkers that cover many of the common properties that engineers check during functional verification.
There is now a VHDL implementation of the 10 most popular checkers, and finer control of X checking on a per-instance basis.
Version 2.0 is backward compatible with previous versions of Accellera OVL.
The Accellera OVL technical committee was formed in early 2005 and the first OVL standard was announced in August 2005.
In addition to creating more checkers and maintaining the standard the committee plans to add features and welcomes new members and contributions.
The Accellera Standard OVL 2.0 standard is available now for download at the Accellera website.
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