New Property Specification Language approved: News from Accellera

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Accellera has approved the Property Specification Language (PSL) standard version 1.1 as an Accellera design verification standard, and has begun the IEEE standardisation process for PSL with the IEEE Corporate Advisory Group (CAG). Accellera's PSL standard addresses the shortcomings of natural language forms of design specification. It allows engineers to capture the functional specifications of logic design - in a way that is unambiguous, effective and concise-using the notion of properties and assertions.

The expressiveness of PSL allows users to easily specify design behaviour with properties, and document design requirements with assertions, saving time and effort in the design verification cycle.

"PSL 1.1 supports the new age of design verification", said Dennis Brophy, Accellera Chairman.

"Effectively, it takes the electronics industry into the era of assertion-based verification, a powerful means for increased confidence in the correctness of a chip or system design prior to fabrication".

"We are very pleased to see the ratification of PSL 1.1 as the next generation of the Accellera property specification language standard", said Erich Marschner, a Senior Architect at Cadence Design Systems and co-chair of the Accellera technical committee that defined PSL.

"PSL and assertion-based verification have been recognised by many as essential for verification of today's increasingly complex designs".

"The completion of PSL 1.1 demonstrates that PSL will continue to grow in capability, to address increasingly challenging verification requirements".

The PSL 1.1 effort focused on refinement of PSL 1.01 and on alignment of syntax and semantics between PSL and SystemVerilog assertions (SVA) where possible.

In addition to correcting errata discovered in PSL 1.01, PSL 1.1 incorporates new features and user-driven enhancements that benefit EDA vendors and users alike.

The PSL extensions subcommittee focused on common requests from users, including the addition of a SystemVerilog flavour, adoption of SVA built-in functions, addition of labels on directives as well as report clauses on certain directives, relaxation of some flavour macros and refinement of operator precedence.

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New Property Specification Language approved

Accellera has approved PSL 1.1 as a design verification standard, and has begun the IEEE standardisation process for PSL with the IEEE Corporate Advisory Group.